CPHA=FIRSTCLOCK, FRF=SPI, CPOL=LOW
Control Register 0. Selects the serial clock rate, bus type, and data size.
| DSS | Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used. 3 (4_BIT_TRANSFER): 4-bit transfer 4 (5_BIT_TRANSFER): 5-bit transfer 5 (6_BIT_TRANSFER): 6-bit transfer 6 (7_BIT_TRANSFER): 7-bit transfer 7 (8_BIT_TRANSFER): 8-bit transfer 8 (9_BIT_TRANSFER): 9-bit transfer 9 (10_BIT_TRANSFER): 10-bit transfer 10 (11_BIT_TRANSFER): 11-bit transfer 11 (12_BIT_TRANSFER): 12-bit transfer 12 (13_BIT_TRANSFER): 13-bit transfer 13 (14_BIT_TRANSFER): 14-bit transfer 14 (15_BIT_TRANSFER): 15-bit transfer 15 (16_BIT_TRANSFER): 16-bit transfer |
| FRF | Frame Format. 0 (SPI): SPI 1 (TI): TI 2 (MICROWIRE): Microwire 3 (RESERVED): This combination is not supported and should not be used. |
| CPOL | Clock Out Polarity. This bit is only used in SPI mode. 0 (LOW): SPI controller maintains the bus clock low between frames. 1 (HIGH): SPI controller maintains the bus clock high between frames. |
| CPHA | Clock Out Phase. This bit is only used in SPI mode. 0 (FIRSTCLOCK): SPI controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line. 1 (SECONDCLOCK): SPI controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line. |
| SCR | Serial Clock Rate. The number of prescaler output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1]). |
| RESERVED | Reserved |